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H8250 Megafunction Universal Asynchronous Receiver/Transmitter
General Description
The H8250 is a standard UART providing 100% software compatibility with the popular Intel 8250 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. Developed for easy reuse in Altera FPGA applications, the H8250 is available optimized for several device families with competitive utilization and performance characteristics.
Features * * * * * *
Capable of running all existing 8250 software Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data Independently controlled transmit, receive, line status and data set interrupts Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock Independent receiver clock input Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn) Fully programmable serial interface characteristics: o o o o 5, 6, 7, or 8 bit characters Even, odd, or no-parity bit generation and detection 1, 11/2, or 2 stop bit generation Baud generation
Symbol
A(2:0) CS RD WR MR CLK DIN(7:0) RCLK SIN CTSn DSRn DCDn RIn H8250
DOUT(7:0) SOUT DDIS RTSn DTRn OUT1n OUT2n INTR BOUDOUTn RXRDY TXRDY
*
* * * *
False start bit detection Complete status register Internal diagnostic capabilities: loopback controls for communications link fault isolation Full prioritized interrupt system controls
Applications * *
Serial or modem computer interface Serial interface within modems and other devices
CAST, Inc.
June 2002
Page 1
CAST H8250 Megafunction Datasheet
Pin Description
Name MR CLK RCLK RD WR CS DIN[7:0] CTSn DSRn DCDn SIN RIn A[2:0] DOUT[7:0] SOUT DDIS RTSn DTRn OUT1n OUT2n INTR BAUDOUTn RXRDY TXRDY Type In In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Polarity High High Falling High Low Low Low Low High Low Low Low Low High Low Low Low Description Master Reset (Asynchronous) Master clock (Should be Global Signal) Receiver clock (Recommended as Global Signal) Read control Write control (Recommended as Global Signal) Chip Select Data Input Bus Clear-to -Send Data Set Ready Data Carrier Detect Serial Input Data Ring Indicator Register Select Data Output Bus Serial Output Data Driver Disable Request-to-Send Data Terminal Ready Output 1 Output 2 Interrupt pending Baud Out Receiver Ready to Receive Transmissions Transmitter Ready to Transmit Data
Register Description
A(2:0) 0 0 0 1 1 2 3 4 5 6 7 Divisor * Latch Access Bit 0 0 1 1 0 X X X X X X Name Receiver Buffer Register Transmitter Holding Register Divisor Latch (LSB) Divisor Latch (MSB) Interrupt Enable Register Interrupt Identification Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Symbol RBR THR DLR DMR IER IIR LCR MCR LSR MSR SR Default (reset) value XX XX 01h 00h 00h 01h 00h 00h 60h 00h 00h No. bits 8 8 8 8 8 8 8 8 8 8 8 Read/ Write R W R/W R/W R/W R R/W R/W R R R/W
*DLAB is the MSB of the Line Control Register
Switching Characteristics
Register Write
The Address (A) and Chip Select (CS) signals are not latched and therefore must be valid throughout the write process. Writing is done at the falling edge of the WR signal.
CAST, Inc.
Page 2
CAST H8250 Megafunction Datasheet
A CS WR DIN
valid
valid
Register Read
The Address (A) and Chip Select (CS) signals are not latched and therefore must be valid throughout the read process. The RD signal is active 1.
A CS RD DOUT DDIS
valid
valid
Write to Transmitter
The timing diagram below depicts the situation where the transmitter is in the process of transmitting a byte which is made up of the Data, Parity and Stop bits. Once the byte is written into the Transmitter Holding Register, the TXRDY signal goes into the off (or high) state. This means that the transmitter is ready for a transfer. As the byte just written starts the transmission (with the Start bit) the TXRDY bit goes low showing that the transmitter is ready for the next byte.
WR SOUT TXRDY
Timing Information for Write Function
DATA PARITY STOP START
CAST, Inc.
Page 3
CAST H8250 Megafunction Datasheet
Read from Receiver
The timing diagram that follows depicts the situation where the receiver is in the process of receiving a byte which is just coming up to the Stop bit. Once a proper Stop bit is received the Byte is placed in the Receiver Buffer Register. This event is signaled to the processor by the RXRDY signal which goes inactive when a byte is awaiting reading. The Receiver Buffer Register must be read before the next byte is received or else an error will be generated.
RD SIN RCLK RXRDY
Timing information for Read Function
STOP
Receiver Synchronization
When the Receiver detects a low state in the incoming data stream it will synchronize to it. After this start edge the UART will wait 1.5*(the normal bit length). This causes the subsequent bits to be read at the middle of its width. This figure depicts this synchronization process.
1.5 bits
First Message bit
Second Message bit
Start bit Detected
Message bit Read
Message bit Read
Receiver Synchronization
CAST, Inc.
Page 4
CAST H8250 Megafunction Datasheet
Block Diagram
A2-A0 CS RD WR MR CLK DDIS D7 - D0 RXBLOCK INTERFACE REGISTERS RXFIFO INTERRUPT CONTROL INTR SIN RCLK
TXFIFO D7 - D0
BAUD RATE BAUDOUT GENERATOR TXBLOCK
SOUT CTSn DSRn
= FIFO Mode
DCDn RIn RTSn DTRn OUT1n OUT2n RXRDY TXRDY
Functional Description
As shown above and explained below, the H8250 includes six major blocks: Interface, Registers, RXBlock, Interrupt Control, Baud Rate Generator, and TXBlock.
Interface
The Interface block is responsible for handling the communications with the processor (or parallel) side of the system. All writing and reading of internal registers is accomplished through this block.
Registers
The Registers block holds all of the device's internal registers. See the Register Description table for details on existing registers and their addresses. Some information comes from the other blocks, but this is all gathered together in the Registers block and made available to all blocks.
CAST, Inc.
Page 5
CAST H8250 Megafunction Datasheet
RXBlock
This is the receiver block. It handles the receiving of the incoming serial word. It is programmable to recognize data widths such as 5, 6, 7 or 8 bits, various parity settings such as even, odd or no parity and different stop bits of 1, 11/2 and 2 bits. It checks for errors in the input data stream such as overrun errors, frame errors, parity errors and break errors. If the incoming word has no problems it is placed in the Receiver Holding register.
Interrupt Control
The Interrupt Control block sends an interrupt signal back to the processor depending on the state of the received and transmitted data. There are various levels of interrupt which can be read from the Interrupt Identification register, which gives the level of interrupt. Interrupts are sent in the condition of empty transmission or receiving buffers, an error in the receiving of a character, or other conditions requiring the attention of the processor.
Baud Rate Generator
This block takes the input clock, CLK, and divides it by a programmed value (from 1 to 216 - 1). This divided clock is then divided by 16 to create the transmission clock called the Baudout clock. This clock can be connected to the input clock (RCLK) to provide it with a proper clock.
TXBlock
The Transmit block handles the transmission of data written to the Transmission Holding register. It adds required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper error handling and receiving.
Component Substitution
The H8250 megafunction is modeled after the Intel 8250. The following points differentiate the H8250 from the Intel device. In order to create a megafunction with the same functions a wrapper is required. A sample wrapper is included.
* * * * * *
No provision is made for a crystal. The CLK input is designed to accept a standard digital input. The bi-directional Data Bus has been split into an input and an output component. In order to use the megafunction with a bi-directional Data Bus, the DDIS signal can be used as the controlling signal for the tri-state drivers. RD2, WR2, CS1 and CS2 have been eliminated. A single signal takes their place. These are RD, WR and CS. The ADSN signal has been removed. The H8250 functions as if the ADSN signal is held low. The included wrapper can be used to add the ADSN functionality latching the address and data buses. The main clock input CLK must be active from power-up. The Baudrate Generator is reset to the 0001h value upon activation of the MR signal. Programming the BRG to 0000h is an illegal value. The minimum value for the BRG is 0001h. The Output Data Bus always shows the value of the last register read.
CAST, Inc.
Page 6
CAST H8250 Megafunction Datasheet
Device Utilization & Performance
Target Device EPF10K30E EP20K30E EP1K10 Speed Grade -1 -1 -1 Utilization LCs 405 403 405 EABs/ESBs 0 0 0 EAB/ESB(bits) 0 0 0 Performance Fmax 126 MHz 136 MHz 125 MHz
Deliverables
Netlist License HDL Source License
* * * * * *
AHDL or EDIF netlist Assignment & Configuration Symbol file Include file Vectors for testing the functionality of the megafunction including expected results Documentation
* * * * * *
VHDL or Verilog RTL source code Testbenches (self checking) Wrapper for pin compatible replacement Vectors for testing functionality Synthesis and simulation scripts Documentation
Megafunction Modifications
The H8250 megafunction can be customized to include:
*
Removing various control interface signals
Please contact CAST for any required modifications
Contact Information
CAST, Inc. 11 Stonewall Court Woodcliff Lake, New Jersey 07677 USA Phone: +1 201-391-8300 Fax: +1 201-391-8694 E-Mail: info@cast-inc.com URL: www.cast-inc.com
Copyright (c) CAST, Inc. 2002, All Rights Reserved. Contents subject to change without notice. CAST, Inc. Page 7

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